When testing memory units in digital circuits, registers in which predeterminable test patterns are stored are usually provided in the digital circuit. Said test patterns comprise different topologies or test topologies, the topologies being able to be varied from test mode to test mode.
One disadvantage of conventional methods for testing memory units in digital circuits is that the test times per chip (digital circuit) increase on account of continually increasing storage capacities. The test times of digital circuits are disadvantageously correlated with the costs for the digital circuit, i.e. long test times increase the price of digital circuits. As the complexity of digital circuits increases, the outlay in creating a digital circuit shifts more and more from pure hardware design toward the implementation of complex test and simulation sequences.
It is thus clearly evident that, to reduce costs in the production and testing of digital circuits, it is necessary in particular to reduce the test times. In order to reduce the test times and thus the test costs, it has already been proposed to increase a parallelism. In digital circuits, in particular in digital memory circuits, internal registers for storing topologies are implemented, different topologies being required in order to realize “worst case” conditions in a memory cell array. The different topologies are stored in the registers of the digital circuit in order to be used in a subsequent test.
In the event of alternating between the different topologies, two different procedures are available, in principle.
(i) Repetition of a register by means of a test mode after testing of memory units in the digital circuit, or